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Modeling and Analysis of Edge Plating for Low-Inductance Board-to-Board Connection in Hierarchical Power Distribution Network
- Alternative Title
- Park Junho
- Author(s)
- 박준호
- Alternative Author(s)
- Park Junho
- Advisor
- 감동근
- Department
- 일반대학원 전자공학과
- Publisher
- The Graduate School, Ajou University
- Publication Year
- 2017-02
- Language
- eng
- Alternative Abstract
- Edge plating has become a well-developed technology, enabling low manufacturing costs for plated edges. Initially, the motivation for developing edge plating was the need to control electromagnetic compatibility (EMC) behavior, the cooling function of a PCB and an advantage for signal integrity. Although edge plating has been available for some time, until now, the use of the edge of the PCB has seldom been considered. While all the other layers of a PCB are well utilized, the third dimension of a PCB, the edge, has been neglected. Therefore, this research investigates the possibilities of using the PCB edge as another routing layer. In this thesis paper, a new package tiling method using edge plating for low inductance board-to-board connection was proposed. The PDN of two packages are usually connected at the board level through vertical interconnects such as vias and solder balls. Alternatively, in proposed methods, they can be connected directly by applying edge plating. The key approach of the proposed package tiling method is that each package is edge plated and plated edges can add a new current path between two packages. Therefore, total loop inductance of proposed package tiling method can be considered as the sum of the original loop inductance and the new loop inductance in parallel. As a result, it causes the reduction of the total loop inductance, resulting in a decrease in SSN. In order to verify the effect of edge plating for low inductance board-to-board connection, two test vehicles, conventional and proposed PDN structures, were designed. The two kinds of the test vehicles were modeled using the balanced TLM method. The microwave simulator (ADS) for the TLM model and 3D EM simulator (HFSS) were used to simulate the self impedance (Z11) of the test vehicle in the frequency range from 10 MHz to 10 GHz. The proposed method has been successfully verified by compared to the total loop inductance of the two structures. The total loop inductance of the conventional and proposed PDN were about 6.98 nH and 2.35 nH through microwave simulator, respectively. The total loop inductance of the conventional and proposed PDN were about 6.68 nH and 2.23 nH through 3D EM simulator, respectively. Also, in order to verify the proposed package tiling methods in time domain, the voltage fluctuation of the test vehicle is simulated. The simulated power supply voltage fluctuation is 680 mV for the test vehicle of the conventional structure, and 180 mV for the test vehicle of the proposed structure. Consequently, it was verified that the proposed package tiling method, edge plating, can significantly reduce the loop inductance of the hierarchical PDN, resulting in a decrease in SSN. Finally, the applications of proposed package tiling method were introduced. First, it was demonstrated that edge plating can also offer a contiguous reference plane for array antenna applications such as 5G massive MIMO antennas, phased-array radar or imaging systems. Second, the practicality of using a proposed package tiling method in actual assemblies was verified. As a result, it was verified that the effect of assembly error in actual assemblies doesn’t have a significant impact in proposed approach. This thesis can successfully propose a new package tiling method for low inductance board-to-board connection from the above results.
- Fulltext
- Appears in Collections:
- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
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