PLC-Code Auto-Generation and Time Barrier in Simulation Based Verification for Error Checking

Abstract

A new approach for PLC-Code auto-generation and its offline verification based on virtual simulation environment would be introduced through the thesis. The method, which involves Timed-Automata in the modeling phase, would be introduced for automatically generated PLC-Code on the working cell level. Thereafter, it would come with the explanation of interlock error checking and handling methods for both automatic and manual modes. The basic idea in this part is to compare the estimated operation time with the real one for each mutual zone, so as to detect the overtimes for calculating the global optimized operation sequence. For verifying the proposed approach, the programs and the result of an experimental simulation were given at the end of the thesis. One thing to notice is that the estimated operation time for each mutual zone is the total time span for the zone being used, but does not include detailed time for single operations. However, each single operation time must be estimated correctly so that the zone’s total time span could be calculated correctly, reasonably and feasibly. Additionally, since the generation process in the thesis adopted the assembly technique [1], there are also possibilities for other sub-processes in the cell to reuse the existing information.