A fully integrated 2.4 GHz CMOS RF transceiver and MCU (System-on-Chip) with short range wake-up function for low-rate wireless personal area network (LR_WPAN) applications in a 0.18-μm CMOS technology is implemented and measured. The chip fully complies with the IEEE 802.15.4 standard. The target applications are small device, like remote-controller, ESL (Electronic Shelf Label), and grasses for 3D TV with particularly tight constraints on power consumption and size. The single chip transceiver incorporates an I/Q modulator and demodulator, an integrated RF synthesizer with a stacked voltage controlled oscillator (VCO), a receiver including the antenna diversity, and passive wake-up circuits using rectifiers.
The receiver has a low-IF architecture with an intermediate frequency of 2 MHz. This architecture allows implementations of the channel filter on wafer. Therefore, an external bulky and expensive filter for the traditional Superheterodyne architecture can be eliminated. The implemented active filter is active RC type and includes an analog integrator and a digital tuning engine to support the realization of an automatic frequency tuning scheme. In order to reduce the power consumption while operating the
receiver mode, the high-Q inductor on wafer and the current reuse topologies are adopted in the LNA and the down-conversion mixer, respectively. An antenna diversity scheme with internal switch is applied for avoiding the dead zone during communication. A fractional frequency synthesizer is designed for local frequency. The VCO's
oscillation frequency sets to 5 GHz, twice of RF carrier frequency to make I/Q signal, prevent pulling effect of VCO and reduce a phase noise of VCO. The VCO is one of the
most critical blocks consuming the power in the transceiver. For the low-power consumption and high-frequency operation, the VCO and the divider-by-2 are stacked.
A Direct-Conversion architecture is used in the transmitter. This architecture is attractive for the following reasons: direct up-conversion produces less mixing product
spurs, it requires fewer filters, and the lower number of parts helps minimize the current consumption.
In order to obtain the ultra low power consumption in sleep-mode, RC-OSC operating under 200 nA, Regulator operating under 200 nA for sleep mode, quick start
block for crystal oscillator, and the passive wake-up circuit are implemented in this transceiver. The power consumption in the sleep and active mode is improved by using a passive wake-up circuits and a stacked VCO, respectively. The transmitter achieves less than 5.0 % error vector magnitude (EVM) at 5 dBm output and the receiver
sensitivity is -101 dBm. The sensitivity of the wake-up block is -29.8 dBm. The current consumption is under 14.3 mA for data receiving mode, 16.7 mA for transmitter and
less than 600 nA for sleep mode from a 1.8 V power supply.
Consequently, I analyzed, implemented, and measured the ultra low-power SoC complied with IEEE 802.15.4. In order to reduce the power consumption of the
transceiver, I used a lots of methods such as the high Q inductor with negative gm, the stacked VCO, the current reuse Mixer, the ultra low power sleep regulator, the ultra low power RC OSC, and no current consumed passive wake-up circuit. The proposed transceiver holds ultra-low power dissipation in the receiving, transmitting, and sleep modes with the reasonable performance because several
techniques are used to reduce power consumption. Therefore, this system can be adopted for ultra-low power systems that require more than 5 years of the operation
using a single Lithium-Ion battery such as electronic shelf labels (ESL), remote controllers, and glasses for 3D TV.