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상수 복소 곱셈기를 적용한 고속 저면적 FFT 프로세서
- Alternative Title
- High speed and Area-efficient FFT processor with Low Complexity Constant Complex Multipliers
- Author(s)
- 신성경
- Advisor
- 선우명훈
- Department
- 일반대학원 전자공학과
- Publisher
- The Graduate School, Ajou University
- Publication Year
- 2015-08
- Language
- kor
- Keyword
- fast Fourier transform processor; FFT processor; Mixed-radix multi-path delay commutator; MRMDC; Orthogonal frequency division multiplexing; OFDM
- Alternative Abstract
- This paper presents a high throughput and area efficient FFT processor for MIMO-OFDM systems based on the multi-path delay commutator (MDC) architecture. This paper proposes new scheduling schemes for reducing the number of complex multipliers and complex constant multipliers. In addition, this paper also proposes a novel structure of the complex constant multiplier which can be implemented without ROM and reduce the hardware complexity. The proposed MDC FFT processors can support 256, 128 and 64-point FFTs. The proposed processors have been designed and implemented with 90-nm CMOS technology. The proposed processors having eight-parallel data paths can achieve a high throughput rate up to 2.4 GS/s at 300 MHz.
- Fulltext
- Appears in Collections:
- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
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