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상수 복소 곱셈기를 적용한 고속 저면적 FFT 프로세서
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 선우명훈 | - |
| dc.contributor.author | 신성경 | - |
| dc.date.accessioned | 2018-11-08T08:21:15Z | - |
| dc.date.available | 2018-11-08T08:21:15Z | - |
| dc.date.issued | 2015-08 | - |
| dc.identifier.other | 20159 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/12965 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :전자공학과,2015. 8 | - |
| dc.description.tableofcontents | Table of Contents Abstract List of Figures List of Tables I. Introduction 1 II. Existing FFT architecture 3 A. Memory based FFT architecture 3 B. Pipelined FFT architecture 3 C. MDC architecture for MIMO-OFDM systems 4 III. Proposed FFT architecture 6 A. Proposed Mixed-radix FFT algorithm 6 B. Proposed FFT architecture 8 i. Input RAM scheduling 10 ii. Stage 1 operations 13 iii. Commutators and delay elements at Stage 2 15 iv. Proposed complex constant multipliers at Stage 2 17 v. Stage 3, 4, and 5 Operations 23 IV. Performance Comparisons 27 V. Conclusion 30 Bibliography 31 | - |
| dc.language.iso | kor | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | 상수 복소 곱셈기를 적용한 고속 저면적 FFT 프로세서 | - |
| dc.title.alternative | High speed and Area-efficient FFT processor with Low Complexity Constant Complex Multipliers | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 일반대학원 | - |
| dc.contributor.department | 일반대학원 전자공학과 | - |
| dc.date.awarded | 2015. 8 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | 705551 | - |
| dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/jsp/common/DcLoOrgPer.jsp?sItemId=000000020159 | - |
| dc.subject.keyword | fast Fourier transform processor | - |
| dc.subject.keyword | FFT processor | - |
| dc.subject.keyword | Mixed-radix multi-path delay commutator | - |
| dc.subject.keyword | MRMDC | - |
| dc.subject.keyword | Orthogonal frequency division multiplexing | - |
| dc.subject.keyword | OFDM | - |
| dc.description.alternativeAbstract | This paper presents a high throughput and area efficient FFT processor for MIMO-OFDM systems based on the multi-path delay commutator (MDC) architecture. This paper proposes new scheduling schemes for reducing the number of complex multipliers and complex constant multipliers. In addition, this paper also proposes a novel structure of the complex constant multiplier which can be implemented without ROM and reduce the hardware complexity. The proposed MDC FFT processors can support 256, 128 and 64-point FFTs. The proposed processors have been designed and implemented with 90-nm CMOS technology. The proposed processors having eight-parallel data paths can achieve a high throughput rate up to 2.4 GS/s at 300 MHz. | - |
- Appears in Collections:
- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
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