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Log-Buffer Aware Cache Replacement Policy for Flash Storage Devices
- Author(s)
- ANWAR, USMAN
- Advisor
- Tae-Sun Chung
- Department
- 일반대학원 컴퓨터공학과
- Publisher
- The Graduate School, Ajou University
- Publication Year
- 2016-08
- Language
- eng
- Keyword
- flash memory; cache management; page replacement policy; flash translation layer; embedded devices
- Alternative Abstract
- In recent times, flash memory has been widely used in embedded devices and enterprise computing environments because of its many advantages, which includes shock resistance, low energy consumption, non-volatile nature and high I/O speed. However, flash memory hardware also possesses characteristics such as erase-before write, a limited number of erase cycles and asymmetric I/O costs among read, write, and erase operations, where the cost of write and erase operations are much higher than that of read operations. Hence, there is the need for the cache-replacement policy in flash-based systems to consider the asymmetric I/O costs. Previous studies on cache management including least recently used (LRU), clean-first LRU (CFLRU) and cold clean-first LRU (CCF-LRU) focused mainly on to reducing the write access to flash memory by evicting clean pages before dirty pages, and they do not consider how the evicted page would be treated by the flash memory. This resulted in performance degradation. Flash aware buffer-management (FAB) tries to evict pages considering the inner structure of flash memory but there are problems related to the high cache-miss ratio and the generation of a large number of write operations to the flash memory. In this paper, we propose a log-buffer aware (LBA) cache-replacement policy that not only tries to reduce the number of write accesses to flash memory as well as the high cache hit ratio, but also evicts pages while considering the log-block associativity problem of log-based flash translation layers (FTLs). Experimental results show that compare to previous studies, the proposed cache-replacement policy is more effective for higher cache-hit ratio and for reducing the garbage-collection overhead of flash memory by increasing the partial merge and switch operations.
- Fulltext
- Appears in Collections:
- Graduate School of Ajou University > Department of Computer Engineering > 3. Theses(Master)
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