비트-직렬 생성기를 활용한 저면적, 높은 처리율을 가지는 LDPC 복호기 구조

Alternative Title
Lee Jea Hack
Author(s)
이재학
Alternative Author(s)
Lee Jea Hack
Advisor
선우명훈
Department
일반대학원 전자공학과
Publisher
The Graduate School, Ajou University
Publication Year
2017-02
Language
eng
Keyword
Area-time complexitybit-serial schemelow-complexity designlow-density parity-check (LDPC) decoderminimum-value generatormin-sum algorithm
Alternative Abstract
Low-density parity-check (LDPC) codes are one of the block coding techniques that can approach the Shannon’s limit within a fraction of a decibel for high block lengths. Recently, LDPC codes have been chosen to be part of many digital communication systems such as IEEE 802.11ad, IEEE 802.15.3c, and 5G telecommunications standard. As the standards are used to provide multi-Gbps throughput in mobile and portable computing devices, the codes allow effective hardware implementation and simultaneously achieve multi-Gbps decoding. The first two minimum values generator is the most complex module of LDPC decoder. This thesis introduces two low-complexity generators. The proposed bit-serial generator reduces the hardware complexity by approximately 26% compared with the existing bit-serial generator. Since the proposed generator requires long latency, a LDPC decoder using the bit-serial scheme is not suitable for multi-Gbps throughput. To achieve short latency, a bitwise generator is proposed, which is constructed using serially connected w bit-serial generators, where w is the word length. The bitwise generator takes only one clock cycle, reducing the hardware complexity by 15%. As the case studies, I have designed two LDPC decoders, flooding and layered schemes, based on a bitwise generator for the 802.11ad standard with the 90-nm CMOS technology. Compared to conventional decoders for 802.11ad, the decoders achieve the most efficient throughput-area ratio.
URI
https://dspace.ajou.ac.kr/handle/2018.oak/11441
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Graduate School of Ajou University > Department of Electronic Engineering > 4. Theses(Ph.D)
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