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고선형 이중 변환 믹서를 사용한 WLAN용 CMOS RF Front-End
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 권익진 | - |
| dc.contributor.author | 오동진 | - |
| dc.date.accessioned | 2018-11-08T07:57:22Z | - |
| dc.date.available | 2018-11-08T07:57:22Z | - |
| dc.date.issued | 2011-02 | - |
| dc.identifier.other | 11619 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/8999 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :전자공학과,2011. 2 | - |
| dc.description.tableofcontents | Chapter 1. Introduction 1 Chapter 2. RF front-end architecture 11 2.1 Heterodyne architecture 11 2.2 Direct conversion architecture 15 2.3 Dual conversion architecture 18 Chapter 3. Circuit design 20 3.1 Design of The Low Noise Amplifier 20 3.2 Design of The Transconductor Stage 25 3.3 Design of The Dual Conversion Passive Mixer 28 3.4 Design of The Divider and The LO Buffer 30 3.5 Simulation result of The Receiver RF Front-End 32 Chapter 4. Measurement Results 33 Chapter 5. Conclusion 39 Publications 40 References 41 국문 요약 44 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | 고선형 이중 변환 믹서를 사용한 WLAN용 CMOS RF Front-End | - |
| dc.title.alternative | Oh, Dong-Jin | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 일반대학원 | - |
| dc.contributor.alternativeName | Oh, Dong-Jin | - |
| dc.contributor.department | 일반대학원 전자공학과 | - |
| dc.date.awarded | 2011. 2 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | 569370 | - |
| dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/jsp/common/DcLoOrgPer.jsp?sItemId=000000011619 | - |
| dc.subject.keyword | RF front-end | - |
| dc.subject.keyword | dual conversion mixer | - |
| dc.subject.keyword | WLAN | - |
| dc.subject.keyword | low power | - |
| dc.description.alternativeAbstract | A low power receiver RF front-end operating in the 5 GHz band according to the IEEE 802.11a WLAN standard is reported. This utilizes the single IF dual conversion architecture for the fully integrated receiver in order to relax the problem of the direct conversion receiver. In the RF front-end, the power consumption is greatly reduced by using the dual conversion current-driven passive mixer with linear transconductor stage. The receiver RF front-end is fabricated with 0.13 um CMOS technology. An IIP3 of -15.8 dBm with a gain of 37.2 dB and a noise figure of 7.1 dB are obtained at 16.8 mW power consumption. | - |
- Appears in Collections:
- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
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