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3-레벨 SiC-NPC 인버터의 부분적 2-레벨 동작을 통한 중성점 전류 저감 기법
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 이교범 | - |
| dc.contributor.author | 송민근 | - |
| dc.date.accessioned | 2022-11-29T02:32:27Z | - |
| dc.date.available | 2022-11-29T02:32:27Z | - |
| dc.date.issued | 2021-02 | - |
| dc.identifier.other | 30505 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/19980 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :전자공학과,2021. 2 | - |
| dc.description.tableofcontents | 제 1 장 서론 1 제 2 장 3-레벨 SiC-NPC 인버터의 중성점 전류 3 2.1 3-레벨 SiC-NPC 인버터의 기본 동작 3 2.2 3-레벨 SiC-NPC 인버터에서 전압 변조 기법에 따른 중성점 전류 생성 4 2.3 3-레벨 SiC-NPC 인버터에서 발생하는 중성점 전류와 DC 링크 커패시터 수명의 관계 7 제 3 장 중성점 전류 저감 기법 8 3.1 3-레벨 SiC-NPC 인버터에서 부분적 2-레벨 동작을 통한 중성점 전류 저감 기법 8 3.2 중성점 전류 저감 기법 적용 시 총 고조파 왜곡률(Total harmonic distortion, THD) 분석 11 제 4 장 시뮬레이션 결과 16 4.1 시뮬레이션 회로도 및 파라미터 16 4.2 중성점 전류 저감 시뮬레이션 17 4.3 전압 변조 기법에 따른 THD 특성 비교 시뮬레이션 19 4.4 전압 변조 기법에 따른 DC 링크 커패시터 손실 분석 20 제 5 장 실험 결과 22 5.1 실험 세트 22 5.2 중성점 전류 저감 기법 실험 결과 23 제 6 장 결론 25 참고문헌 26 | - |
| dc.language.iso | kor | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | 3-레벨 SiC-NPC 인버터의 부분적 2-레벨 동작을 통한 중성점 전류 저감 기법 | - |
| dc.title.alternative | Neutral-Point Current Reduction Method Through Partial Two-Level Operation in Three-Level SiC-NPC Inverters | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 일반대학원 | - |
| dc.contributor.alternativeName | Min-Geun Song | - |
| dc.contributor.department | 일반대학원 전자공학과 | - |
| dc.date.awarded | 2021. 2 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | 1202764 | - |
| dc.identifier.uci | I804:41038-000000030505 | - |
| dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/common/orgView/000000030505 | - |
| dc.subject.keyword | Neutral-point clamped inverters | - |
| dc.subject.keyword | Neutral-point current | - |
| dc.subject.keyword | Reliability | - |
| dc.subject.keyword | Silicon-carbide devices | - |
| dc.subject.keyword | Three-level inverters | - |
| dc.description.alternativeAbstract | This thesis proposes a neutral-point current reduction method in three-level silicon carbide neutral-point clamped (SiC-NPC) inverters. The SiC-NPC inverters have the same configuration as standard NPC inverters and consist only the SiC devices. The neutral-point current is the current flowing through the DC-link capacitor in three-level inverters. This neutral-point current occurs depend on voltage modulation scheme in three-level inverters and this current affects lifetime of the DC-link capacitors. The lifetime of DC-link capacitors is closely related to reliability of inverters because the capacitor failure is one of the major causes of equipment failure. To reduce this neutral-point current, the thesis proposes the new voltage modulation scheme based on the partial two-level operation. In the three-level inverters, the neutral-point current occurs when the inverter is operated with three voltage level (positive, neutral and negative), but does not occur when the inverter is operated with two voltage level (positive and negative). Therefore, the neutral-point current is reduced by the proper combination of two-level and three-level operations. The proposed method is verified by simulation and experiment. | - |
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- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
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