repository
극 부호를 위한 저지연 Bit-Flipping Successive-Cancellation 복호
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 선우명훈 | - |
| dc.contributor.author | 김승용 | - |
| dc.date.accessioned | 2022-11-29T02:32:04Z | - |
| dc.date.available | 2022-11-29T02:32:04Z | - |
| dc.date.issued | 2020-02 | - |
| dc.identifier.other | 29891 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/19554 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :전자공학과,2020. 2 | - |
| dc.description.tableofcontents | I. Introduction 1 II. Review of Polar Codes 4 A. Encoding of Polar Codes 4 B. Successive-Cancellation Decoding 4 C. Successive-Cancellation List Decoding 5 D. Flip Decoding 6 III. Proposed SCF Decoding 8 A. First Error Bit Occurrence Frequency 8 B. Encoding of Proposed SCF 10 C. Decoding of Proposed SCF 12 IV. Simulation Results and Comparisons 14 V. Conclusion 18 Bibliography 19 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | 극 부호를 위한 저지연 Bit-Flipping Successive-Cancellation 복호 | - |
| dc.title.alternative | Kim, Seung Yong | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 일반대학원 | - |
| dc.contributor.alternativeName | Kim, Seung Yong | - |
| dc.contributor.department | 일반대학원 전자공학과 | - |
| dc.date.awarded | 2020. 2 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | 1138625 | - |
| dc.identifier.uci | I804:41038-000000029891 | - |
| dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/common/orgView/000000029891 | - |
| dc.subject.keyword | Cyclic Redundancy Check | - |
| dc.subject.keyword | Polar Codes | - |
| dc.subject.keyword | Successive-Cancellation | - |
| dc.subject.keyword | Successive-Cancellation Flip | - |
| dc.description.alternativeAbstract | The Successive-cancellation (SC) algorithm of polar codes used a sequential decoding process that decodes one bit at a time. Thus, polar codes can propagate the error if an error occurs. To solve this problem, the SC-Flip (SCF) decoding method was proposed, which can improves the error correction performance by flipping the first error bit. However, it is not suitable for hardware implementation because the latency significantly increases in the worst case. In this paper, we propose an efficient decoding method to reduce the latency of the conventional SCF decoding algorithm. The proposed decoding method divides the information bits into several sub-frames and performs a flip decoding process only within the corresponding sub-frame through cyclic redundancy check (CRC) detection for each sub-frame. As a result of Matlab simulation, the proposed decoding method shows that the average clock cycles are reduced by up to 67.3% at 1dB and up to 10.53% at 2dB while maintaining the high error correction performance of the existing SCF decoding. | - |
- Appears in Collections:
- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
- Files in This Item:
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
-
- License
- STATISTICS
- Total Visit :3,867,593
- Total Download :1,953
- Today View :4,371
