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A Dynamic Setting for Flash Translation Layer
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 정태선 | - |
| dc.contributor.author | 채석주 | - |
| dc.date.accessioned | 2022-11-29T02:32:00Z | - |
| dc.date.available | 2022-11-29T02:32:00Z | - |
| dc.date.issued | 2020-02 | - |
| dc.identifier.other | 29581 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/19476 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :컴퓨터공학과,2020. 2 | - |
| dc.description.tableofcontents | Chapter 1 Introduction 1 Chapter 2 Background and Related Work 4 2.1 Nand flash memory 4 2.2 FTL 5 2.3 Related Work 7 Chapter 3 Problem Statement 10 3.1 Operations of merge 10 3.2 Associativity between a data block and a log block 12 3.3 Space utilization of a data block 14 Chapter 4 System Design 16 4.1 System architecture 16 4.2 Increase of a switch merge and Decrease of a partial merge 16 4.3 Adjust associativity dynamically 19 4.4 Increasing space utilization of a data block 22 Chapter 5 Evaluation 25 5.1 Experiment setup 25 5.2 Workloads 26 5.3 Experimental results 26 Chapter 6 Conclusion 30 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | A Dynamic Setting for Flash Translation Layer | - |
| dc.title.alternative | Suk-Joo Chae | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 일반대학원 | - |
| dc.contributor.alternativeName | Suk-Joo Chae | - |
| dc.contributor.department | 일반대학원 컴퓨터공학과 | - |
| dc.date.awarded | 2020. 2 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | 1138498 | - |
| dc.identifier.uci | I804:41038-000000029581 | - |
| dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/common/orgView/000000029581 | - |
| dc.subject.keyword | Flash Memory | - |
| dc.description.alternativeAbstract | Flash memory has been utilized in a lot of mobile computing devices, including smartphones and tablets because of its fast access speed, non-volatility, low power consumption, and resistance to shocks. Because of the hardware characteristics of the flash memory that differ from hard disk drives (HDD), a flash translation layer (FTL) has been introduced to make the flash memory device appear as block device to its host the equal as HDD does. However, due to the out-of-place-update feature of flash memory, fresh blocks need to be constantly availed through garbage collection (GC) of invalid pages which causes an expensive overhead. In the previous hybrid-level mapping schemes, there are three problems that cause GC overhead. First, a partial merge causes more page copies than a switch merge. However, many authors only approaches reducing a full merge. Second, the associativity between a data block and a log block makes the space utilization of the log block lower, and it also generates a very expensive full merge. Third, the space utilization of the data block is low since data block which has many free pages is merged. Therefore, in this thesis, we propose an FTL approach (DSFTL) that uses many SW (Sequential Write) log blocks which increase switch merge and decrease partial merge. DSFTL can dynamically manage the data blocks and log blocks to decrease operations of erase and expensive full merge. Also, our scheme prevents a data block with many free pages from being merged to increase the space utilization of the data block. Our extensive experimental results prove that our proposed approach (DSFTL) decreases the erase count and increase switch merge of flash memory devices employing hybrid-level mapping algorithms. As a result, DSFTL decreases the garbage collection overhead. | - |
- Appears in Collections:
- Graduate School of Ajou University > Department of Computer Engineering > 3. Theses(Master)
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