FTL-aware hot data identification scheme for flash memory

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dc.contributor.advisorTae-sun Chung-
dc.contributor.authorAyele Sololia Gudeta-
dc.date.accessioned2019-10-21T07:24:06Z-
dc.date.available2019-10-21T07:24:06Z-
dc.date.issued2014-08-
dc.identifier.other17314-
dc.identifier.urihttps://dspace.ajou.ac.kr/handle/2018.oak/18575-
dc.description학위논문(석사)--아주대학교 Graduate School :컴퓨터공학과,2014. 8-
dc.description.tableofcontentsTable of Contents LIST OF FIGURES ...................................................................................................... 4 LIST OF TABLES ........................................................................................................ 4 LIST OF ACRONYMS ................................................................................................ 5 1. INTRODUCTION .................................................................................................... 6 2. BACKGROUND INFORMATION ........................................................................ 9 2.1. SYSTEM ARCHITECTURE OF FLASH MEMORY........................................................ 9 2.2. BLOOM FILTER .................................................................................................... 12 3. RELATED WORKS ............................................................................................... 14 3.1. BLOOM FILTER-BASED HOT AND COLD DATA IDENTIFICATIONS ........................ 14 3.2. PROBLEMS AND OBSERVATIONS .......................................................................... 16 4. PROPOSED SCHEME .......................................................................................... 18 4.1. RABIN’S HASHING TECHNIQUE ........................................................................... 18 4.2. MODELING RABIN’S FINGERPRINTING SCHEME FOR FLASH MEMORY ................ 20 4.2.1. Hashing Using Random Polynomials .......................................................... 20 4.3. DEFINING THRESHOLD ........................................................................................ 22 5. PERFORMANCE EVALUATION ....................................................................... 29 5.1. ANALYTICAL STUDY ........................................................................................... 29 5.2. EXPERIMENTAL DESIGN ...................................................................................... 31 6. CONCLUSION ....................................................................................................... 36 REFERENCES ........................................................................................................... 37-
dc.language.isoeng-
dc.publisherThe Graduate School, Ajou University-
dc.rights아주대학교 논문은 저작권에 의해 보호받습니다.-
dc.titleFTL-aware hot data identification scheme for flash memory-
dc.typeThesis-
dc.contributor.affiliation아주대학교 일반대학원-
dc.contributor.department일반대학원 컴퓨터공학과-
dc.date.awarded2014. 6-
dc.description.degreeMaster-
dc.identifier.localId652548-
dc.identifier.urlhttp://dcoll.ajou.ac.kr:9080/dcollection/jsp/common/DcLoOrgPer.jsp?sItemId=000000017314-
dc.description.alternativeAbstractHot data identification in flash memory is of great interest because it significantly affects the garbage collection and wear-leveling performance. Presently, certain hot and cold data classification schemes based on Bloom Filters have been proposed. Although Bloom Filters are efficient in most cases, there is a significant trade-off between false positive rates, which are the result of hash value collisions, and memory utilization. In this paper, we suggest a better data categorization mechanism that is based on a hashing technique called Fingerprinting by Random Polynomials with the aim of reducing false positive rates and achieving lower memory consumption compared to the Bloom Filter based schemes. We also introduce a new methodology for classifying write requests by linking the definition of hot and cold write requests to the flash memory software layer, the flash translation layer characteristics. Our approach improves space utilization by representing each logical block number by one counter in the hash table, and achieves an extremely low error rate by choosing the degree of the hash function based on the address space of the flash memory. In addition, we achieved lower false identification rates. We demonstrate the performance using mathematical analysis and trace-driven simulation.-
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Graduate School of Ajou University > Department of Computer Engineering > 3. Theses(Master)
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