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과도 응답 성능을 개선한 저전력 전압 레귤레이터 설계
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 권익진 | - |
| dc.contributor.author | 이성환 | - |
| dc.date.accessioned | 2019-04-01T16:41:38Z | - |
| dc.date.available | 2019-04-01T16:41:38Z | - |
| dc.date.issued | 2019--2 | - |
| dc.identifier.other | 28872 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/15117 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :전자공학과,2019. 2 | - |
| dc.description.tableofcontents | Chapter 1. Introduction 1 Chapter 2. Conventional LDO regulator 2 Chapter 3. Proposed LDO regulator 5 Chapter 4. Simulation Results 14 Chapter 5. Measurement Results 20 Chapter 6. Conclusion 34 Publications 35 References 36 국문 요약 38 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | 과도 응답 성능을 개선한 저전력 전압 레귤레이터 설계 | - |
| dc.title.alternative | Sung-hwan Lee | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 일반대학원 | - |
| dc.contributor.alternativeName | Sung-hwan Lee | - |
| dc.contributor.department | 일반대학원 전자공학과 | - |
| dc.date.awarded | 2019. 2 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | 905351 | - |
| dc.identifier.uci | I804:41038-000000028872 | - |
| dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/common/orgView/000000028872 | - |
| dc.description.alternativeAbstract | This paper proposes an external capacitor-less low-dropout (LDO) regulator with undershoot and settling time reduction technique for fast transient response. In the proposed LDO, a feedback capacitor is applied instead of a complicated voltage-spike detection circuit to reduce undershoot voltage and settling time without consuming additional quiescent current. When the undershoot voltage occurs in the load transient response, the gate charging current of the pass transistor is rapidly increased by the current flowing in the feedback capacitor to reduce the undershoot voltage. When the overshoot voltage occurs, the gate charging current to reduce the settling time. The proposed LDO regulator is implemented with a 0.18 μm CMOS process and consumes a quiescent current of 3.0 μA at a minimum load current of 0.1 mA and 230 μA at a maximum load current of 50 mA. Compared with the conventional LDO regulator, the proposed LDO regulator reduces the undershoot voltage by 53.3 % and the settling time by 55.5 % without consuming additional quiescent current. | - |
- Appears in Collections:
- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
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