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연속 제거 리스트 복호기를 위한 노드 공유된 빠른 다중 비트 결정 방법
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 선우명훈 | - |
| dc.contributor.author | 정서린 | - |
| dc.date.accessioned | 2019-04-01T16:40:21Z | - |
| dc.date.available | 2019-04-01T16:40:21Z | - |
| dc.date.issued | 2019-02 | - |
| dc.identifier.other | 28630 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/14856 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :전자공학과,2019. 2 | - |
| dc.description.tableofcontents | Abstract i List of Figures ii List of Tables v I. Introduction 1 II. Review of Polar Codes 4 A. Polar Codes 4 B. Successive-Cancellation(SC) Decoding 6 C. SC List Decoding 7 D. Simplified-SCL Decoding 7 E. Multibit Decision Method 8 III. Proposed Multibit Decision with Shared Nodes and Short-tailed Sorter 9 A. R0-REP Node 10 B. R1-SPC Node 11 C. Else Node 13 D. Short-tailed Sorter 16 IV. Fast Multibit Decision Decoder Architecture 17 A. Proposed Architecture 17 B. R0-REP Node 19 C. R1-SPC Node 19 D. Else Node 20 V. Implementation Results and Comparisons 21 VI. Conclusions 24 Bibliography 25 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | 연속 제거 리스트 복호기를 위한 노드 공유된 빠른 다중 비트 결정 방법 | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 일반대학원 | - |
| dc.contributor.department | 일반대학원 전자공학과 | - |
| dc.date.awarded | 2019. 2 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | 905488 | - |
| dc.identifier.uci | I804:41038-000000028630 | - |
| dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/common/orgView/000000028630 | - |
| dc.description.alternativeAbstract | Successive-cancellation list (SCL) is a decoding algorithm for polar codes that require high latency owing to serial operations. While several algorithms have been proposed to improve this latency with additional circuits, the area was enlarged. In this paper, we propose a fast multibit decision method with small area based SCL decoding algorithm. First, multiple bits can be determined to consume only fewer clock cycles using nodes represented by the information bits and frozen bits. The nodes called shared nodes in this paper. There are two combined nodes with similar bit patterns for hardware efficiency and one node with the rest bits grouped into 8 bits for fast multibit decision. In addition, a short-tailed sorter is proposed to reduce the critical path delay. As a large number of path metrics cause sorter delays, the proposed sorter can achieve high throughput with a small area. The proposed (1024, 512) SCL decoder showed negligible performance degradation in the simulation and was synthesized using 65 nm CMOS technology. The proposed decoder achieves about 1.3Gbps with a small area. As a result, area-throughput efficiency is the best among decoders above 1Gbps. | - |
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- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
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