인쇄 회로 기판에서의 전원단 잡음 분석 및 개선 연구

DC Field Value Language
dc.contributor.advisor이해영-
dc.contributor.author이신영-
dc.date.accessioned2018-11-14T06:13:14Z-
dc.date.available2018-11-14T06:13:14Z-
dc.date.issued2004-
dc.identifier.other3790-
dc.identifier.urihttps://dspace.ajou.ac.kr/handle/2018.oak/14621-
dc.description학위논문(석사)--亞洲大學校 大學院 :電子工學,2004-
dc.description.tableofcontentstest-
dc.language.isokor-
dc.publisherThe Graduate School, Ajou University-
dc.rights아주대학교 논문은 저작권에 의해 보호받습니다.-
dc.title인쇄 회로 기판에서의 전원단 잡음 분석 및 개선 연구-
dc.typeThesis-
dc.contributor.affiliation아주대학교 일반대학원-
dc.contributor.department일반대학원 전자공학과-
dc.date.awarded2004. 2-
dc.description.degreeMaster-
dc.identifier.localId563889-
dc.identifier.urlhttp://dcoll.ajou.ac.kr:9080/dcollection/jsp/common/DcLoOrgPer.jsp?sItemId=000000003790-
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Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
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