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최적화된 스위칭 기법을 적용한 3-레벨 T-type 인버터의 직류단 전류 리플 저감 방법
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 이교범 | - |
| dc.contributor.author | 원인정 | - |
| dc.date.accessioned | 2018-11-08T08:23:30Z | - |
| dc.date.available | 2018-11-08T08:23:30Z | - |
| dc.date.issued | 2017-08 | - |
| dc.identifier.other | 25633 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/13514 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :전자공학과,2017. 8 | - |
| dc.description.tableofcontents | CHAPTER I. INTRODUCTION 1 CHAPTER II. DC-LINK CURRENT RIPPLE WITH SWITCHING PATTERN 4 2.1 Simplified SVPWM method 4 2.2 Switching State on DC-link Current Ripple 7 CHAPTER III. SWITCHING STRATEGY FOR THE DC-LINK CURRENT RIPPLE REDUCTION 9 3.1 Proposed Switching Scheme 9 3.2 Neutral-point Voltage Balance 13 CHAPTER IV. SIMULATION RESULTS 15 CHAPTER V. EXPERIMENTAL RESULTS 19 CHAPTER VI. CONCLUSIONS 24 REFERENCES 25 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | 최적화된 스위칭 기법을 적용한 3-레벨 T-type 인버터의 직류단 전류 리플 저감 방법 | - |
| dc.title.alternative | A DC-link Current Ripple Reduction Method with Optimized Switching Scheme in Three-level T-type Inverters | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 일반대학원 | - |
| dc.contributor.department | 일반대학원 전자공학과 | - |
| dc.date.awarded | 2017. 8 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | 788727 | - |
| dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/jsp/common/DcLoOrgPer.jsp?sItemId=000000025633 | - |
| dc.subject.keyword | 3-레벨 T-type 인버터 | - |
| dc.subject.keyword | 직류단 전류 리플 저감 | - |
| dc.description.alternativeAbstract | This paper presents an optimized switching strategy for DC-link capacitor current ripple reduction. The large electrolytic capacitors are commonly used at the DC-link of power electronics applications to stabilize the DC-link voltage and supply power for the inverter. The most important factor for designing the DC-link capacitor is allowable current ripple of the capacitor. The DC-link over-ripple causes a high heat-loss, shortened lifespan, and low stability and reliability. Therefore, the large passive components are typically used to reduce the current ripple. However, these passive components lead to a bulky size and slow dynamic response. This paper proposes a new switching scheme to reduce the DC-link capacitor current ripple without any additional hardware or complex calculations. In addition, the common mode voltage and leakage current are decreased by proposed switching method. The efficacy of the proposed method is verified using simulations and experimental results with a three-level T-type inverter. | - |
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- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
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