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A Recovery Technique for Flash Memory Using Shadow Paging
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | Tea-Sun Chung | - |
| dc.contributor.author | ABDULGHAFUR, ALAHMADI ABDULHADI | - |
| dc.date.accessioned | 2018-11-08T08:21:57Z | - |
| dc.date.available | 2018-11-08T08:21:57Z | - |
| dc.date.issued | 2015-08 | - |
| dc.identifier.other | 20768 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/13155 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :컴퓨터공학과,2015. 8 | - |
| dc.description.tableofcontents | 1. Introduction 1 2. Related work 3 2.1 Flash Translation Layer (FTL) 4 2.2 FTL characteristics 5 3. Background 7 3.1Address mapping schemes 7 3.2 Merge Operations 11 3.3 Memory requirements 12 3.4 Map block method 13 4. Proposed Technique (RTUSP) 15 4.1 Key Idea 15 4.2 Revisit Map Block Method 16 4.3 Revisit Shadow Paging 22 4.4 RTUSP 24 4.5 Comparison 27 5. Conclusion 31 6. References 32 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | A Recovery Technique for Flash Memory Using Shadow Paging | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 일반대학원 | - |
| dc.contributor.department | 일반대학원 컴퓨터공학과 | - |
| dc.date.awarded | 2015. 8 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | 705403 | - |
| dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/jsp/common/DcLoOrgPer.jsp?sItemId=000000020768 | - |
| dc.subject.keyword | Flash memory | - |
| dc.subject.keyword | Storage management | - |
| dc.subject.keyword | Power of recovery | - |
| dc.subject.keyword | Power failure | - |
| dc.description.alternativeAbstract | Flash memory is a constantly-powered nonvolatile semi-conductor device that has the advantages of small size, fast access, low power consumption, convenient portability, shock resistance, data retention after a power off, random access, and heat dissipation. Flash memory is currently being integrated with different embedded system devices such as in digital cameras, smart phones, PDAs, and sensor devices. However, as flash memory has special characteristics like wear-leveling and “erase-before-write”, a FTL (flash translation layer) at software layer should be included. Though even the power off recovery is very important in portable devices most FTL algorithms did not consider the power off recovery scheme. In this paper we proposed a Recovery Technique for flash memory Using Shadow Paging (RTUSP) for flash memory based storage devices. To overcome the sudden power off, our idea saves the map block information in two tables: the first one is original and the second one is a copy one. Our technique improves the capacity of flash memory and is compatible the existing FTL algorithms. | - |
- Appears in Collections:
- Graduate School of Ajou University > Department of Computer Engineering > 3. Theses(Master)
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