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Special Graduate Schools
Graduate School of Science and Technology
Department of Industrial Engineering
3. Theses(Master)
반도체 생산라인에서 시뮬레이션을 이용한 병목공정 탐지 프레임워크
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 박상철 | - |
| dc.contributor.author | Yang Ka Ram | - |
| dc.date.accessioned | 2018-11-08T08:18:23Z | - |
| dc.date.available | 2018-11-08T08:18:23Z | - |
| dc.date.issued | 2015-02 | - |
| dc.identifier.other | 18855 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/12658 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :산업공학과,2015. 2 | - |
| dc.description.tableofcontents | Contents Ⅰ Introduction 1 1. Semiconductor production 1 2. Research motive and purpose 9 3. Related research 12 4. Composition of thesis 15 Ⅱ Pegging and simulation 16 1. Pegging 16 2. Simulation 18 Ⅲ Bottleneck process detection framework 20 1. Framework structure 20 2. Dispatching Rule 25 3. FAB Modeling 26 4. FAB Data Set 30 5. Realization 33 Ⅳ Experiment 34 1. Experiment 1 35 2. Experiment 2 38 3. Experiment 3 41 Ⅴ Conclusion 44 Bibliography 45 Abstract 48 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | 반도체 생산라인에서 시뮬레이션을 이용한 병목공정 탐지 프레임워크 | - |
| dc.title.alternative | Ka ram Yang | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 일반대학원 | - |
| dc.contributor.alternativeName | Ka ram Yang | - |
| dc.contributor.department | 일반대학원 산업공학과 | - |
| dc.date.awarded | 2015. 2 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | 695543 | - |
| dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/jsp/common/DcLoOrgPer.jsp?sItemId=000000018855 | - |
| dc.subject.keyword | Semiconductor | - |
| dc.subject.keyword | wafer FAB | - |
| dc.subject.keyword | Simulation | - |
| dc.subject.keyword | bottleneck detection | - |
| dc.description.alternativeAbstract | A semiconductor prices fluctuate due to changing supply and demand for semiconductors. Research for better productivity has become important as well as research for semiconductor technologies as production processes have become complicated. In this regard, this paper suggests a bottleneck detection framework to enhance productivity in semiconductors. The semiconductor wafer FAB has various features such as the use of re-entrant production methods or batch equipment. Improving bottlenecks is crucial for better productivity in the semiconductor wafer FAB. This paper defines bottleneck problems and classifies actual bottlenecks for improvement. Furthermore, it proposes a bottleneck detection framework based on a simulation to detect actual bottlenecks. This paper investigates actual bottlenecks in a production process perspective and aims to detect bottlenecks to improve productivity. Actual bottlenecks do not refer to those producing a small number of products or having a large number of WIP, but rather refer to those failing to meet targets in spite of their potentials. They also can have better productivity than other bottlenecks when problems are resolved. Equipment capacity is fixed. Facilities are able to meet target move rates but processes sometimes fail to keep up with facilities leading to missing target moves. Therefore, this study aims to investigate bottleneck steps rather than to bottleneck facilities. | - |
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