Efficient Thread Mapping For Heterogeneous Multi-Core Systems

DC Field Value Language
dc.contributor.advisorYoung June Choi-
dc.contributor.authorTHOMAS MEZMUR BIRHANU-
dc.date.accessioned2018-11-08T08:16:03Z-
dc.date.available2018-11-08T08:16:03Z-
dc.date.issued2016-02-
dc.identifier.other21934-
dc.identifier.urihttps://dspace.ajou.ac.kr/handle/2018.oak/12062-
dc.description학위논문(석사)--아주대학교 일반대학원 :컴퓨터공학과,2016. 2-
dc.description.tableofcontents1 Introduction 1 2 Literature Review 4 3 Methodology 6 3.1 Assumptions 6 3.2 Heterogeneity Measure 6 3.3 Fastest-Thread-Fastest-Core Scheduler 7 3.3.1 Homogenization 8 3.3.2 Normalization 9 4 Results 13 4.1 ESESC Simulator 13 4.2 Experimentation 14 5 Conclusion 19-
dc.language.isoeng-
dc.publisherThe Graduate School, Ajou University-
dc.rights아주대학교 논문은 저작권에 의해 보호받습니다.-
dc.titleEfficient Thread Mapping For Heterogeneous Multi-Core Systems-
dc.typeThesis-
dc.contributor.affiliation아주대학교 일반대학원-
dc.contributor.department일반대학원 컴퓨터공학과-
dc.date.awarded2016. 2-
dc.description.degreeMaster-
dc.identifier.localId739399-
dc.identifier.urlhttp://dcoll.ajou.ac.kr:9080/dcollection/jsp/common/DcLoOrgPer.jsp?sItemId=000000021934-
dc.subject.keywordComputer Engineering-
dc.description.alternativeAbstractThis paper proposes a thread scheduling mechanism primed for heterogeneously configured multicore systems. Our approach uses a relativistic sense of mapping running threads CPU utilization with the appropriate core that can potentially deliver the actual needed capacity. The paper also introduces a mapping algorithm that is able to map threads to cores in an O(NLogM) time complexity, where N is the number of cores and M is the number of types of cores. In addition to that we also introduced a method of profiling heterogeneous architectures based on the discrepancy between the performances of individual cores. Our heterogeneity aware scheduler was able to speedup processing by 52.62% and save power by 2.22% as compared to Linux’s default CFS scheduler.-
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Graduate School of Ajou University > Department of Computer Engineering > 3. Theses(Master)
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