반절연 기판위에 제작된 수평형 탄화규소 전력소자
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 조중열 | - |
dc.contributor.author | 김형우 | - |
dc.date.accessioned | 2018-11-08T08:14:43Z | - |
dc.date.available | 2018-11-08T08:14:43Z | - |
dc.date.issued | 2018-02 | - |
dc.identifier.other | 26823 | - |
dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/11782 | - |
dc.description | 학위논문(박사)--아주대학교 일반대학원 :전자공학과,2018. 2 | - |
dc.description.abstract | 에피층(Epitaxial layer)의 성장 없이 on-axis를 가지는 탄화규소 반절연 기판만을 사용한 수평형 탄화규소 전력소자에 관해 연구하였다. 소자의 제작에 앞서 반절연 기판이 이온주입 공정에 미치는 영향을 확인하기 위해 반절연 기판을 사용하여 이온주입 실험을 수행하고 결과를 분석하였다. 또한 현재 상용화되어 있는 반절연 기판 중에서 소자의 제작에 적합한 반절연 기판의 선택을 위해 HPSI (High Purity Semi-Insulating) 및 VDSI (Vanadium Doped Semi-Insulating) 기판을 이용해 에피층 없이 수평형 p-i-n 다이오드를 설계 및 제작하고 전기적 특성을 분석하였다. 상기와 같은 이온주입 실험과 수평형 p-i-n 다이오드 제작 및 분석 결과를 바탕으로 HPSI 기판을 사용하여 반절연 기판만을 사용한 수평형 탄화규소 MOSFET를 설계 및 제작하고 전기적 특성을 분석하였다. 설계 및 제작된 수평형 탄화규소 MOSFET의 경우 반절연 기판만을 사용하였기 때문에 p-base 영역과 n+ drain 영역 사이에 이온주입을 통해 형성되는 CPL (Current Path Layer)을 드리프트(Drift) 영역으로 채용함으로써 기존 MOSFET에서의 드리프트 층을 대체하였다. 제작된 수평형 탄화규소 MOSFET의 경우 on-axis 반절연 기판의 사용과 CPL 영역 변수의 최적화를 통해 p-base에서 n+ drain까지의 거리 LCPL = 20 ㎛인 경우에 1093 V의 항복전압과 89.8 mΩ·㎠의 온-저항(Specific on-resistance)를 나타내었다. 또한 실험을 통해 추출된 채널 이동도(Effective channel mobility)의 경우도 이동도 향상을 위한 특별한 기법의 적용이 없이 21.7 ㎠/V·s를 나타내었다. 일반적으로 전력용 반도체 소자의 성능 지표로 많이 사용되는 FoM (Figure-of-Merit, BV2/RON,SP)의 경우도 13.3 ㎿/㎠로 비교적 높은 값을 나타내었다. | - |
dc.description.tableofcontents | 제1장 서론 ················································································ 1 제1절 연구의 배경 및 연구 방향 ··········································· 1 제2절 논문의 구성 ··································································· 9 제2장 반절연 기판을 이용한 고농도 ····································10 이온주입 연구 제1절 시뮬레이션을 이용한 이온주입 조건 설정 ·············· 11 1. SRIM 시뮬레이션을 이용한 이온주입 조건 설계 ········· 11 2. ATHENA 시뮬레이션을 이용한 이온주입 조건 설계 ··· 14 3. Wafer 온도 변화에 따른 이온주입 조건 시뮬레이션 ··· 18 제2절 고농도 이온주입 실험 및 결과 ·································· 23 1. SIMS 분석을 이용한 시뮬레이션 결과와 실험 결과 비교 분석 ························································································ 23 제3절 반절연 탄화규소 기판에서의 활성화율 ···················· 31 제3장 반절연 기판을 이용한 수평형 다이오드 ·················· 36 제1절 수평형 탄화규소 다이오드 설계 및 시뮬레이션 ······································································· 37 1. 수평형 탄화규소 p-i-n 다이오드 설계 ···························· 37 2. 시뮬레이션 결과 ································································· 43 제2절 수평형 탄화규소 다이오드의 특성 분석 ··················· 49 1. 수평형 탄화규소 p-i-n 다이오드 제작 ···························· 49 2. 실험 결과 및 분석 ······························································· 51 제4장 반절연 기판을 이용한 4H 탄화규소 수평형 MOSFET ······································································ 61 제1절 4H 탄화규소 수평형 MOSFET 구조 및 동작 원리 ········································································· 63 1. 4H 탄화규소 수평형 MOSFET 구조 및 동작 원리 ········ 63 2. 4H 탄화규소 수평형 MOSFET의 개발 동향 ··················· 68 제2절 4H 탄화규소 수평형 MOSFET의 설계 및 시뮬레이션을 통한 특성 분석 ····································· 78 1. 4H 탄화규소 수평형 MOSFET 설계 ································ 78 2. 4H 탄화규소 수평형 MOSFET 시뮬레이션 및 분석 ····· 80 제3절 4H 탄화규소 수평형 MOSFET 제작 및 분석 ··················································································· 92 1. 4H 탄화규소 수평형 MOSFET 제작 ······························· 92 2. 순방향 및 역방향 측정 결과 및 분석 ······························ 97 제5장 결론 ············································································· 109 참고문헌 ················································································· 112 부록 ························································································· 122 Abstract ·················································································· 144 | - |
dc.language.iso | kor | - |
dc.publisher | The Graduate School, Ajou University | - |
dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
dc.title | 반절연 기판위에 제작된 수평형 탄화규소 전력소자 | - |
dc.title.alternative | Lateral SiC Power Devices on Semi-insulating Substrate | - |
dc.type | Thesis | - |
dc.contributor.affiliation | 아주대학교 일반대학원 | - |
dc.contributor.alternativeName | Kim Hyoung Woo | - |
dc.contributor.department | 일반대학원 전자공학과 | - |
dc.date.awarded | 2018. 2 | - |
dc.description.degree | Doctoral | - |
dc.identifier.localId | 800868 | - |
dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/jsp/common/DcLoOrgPer.jsp?sItemId=000000026823 | - |
dc.subject.keyword | 탄화규소 | - |
dc.subject.keyword | 수평형소자 | - |
dc.subject.keyword | 전력소자 | - |
dc.subject.keyword | MOSFET | - |
dc.subject.keyword | 반절연 | - |
dc.description.alternativeAbstract | In this thesis, silicon carbide (SiC) lateral power device fabricated on an on-axis semi-insulating substrate without using an epitaxial layer is investigated. Prior to the device fabrication, ion implantation were performed by using semi-insulating substrate to investigate the effect of the semi-insulating substrate on the ion implantation process, and the results were analyzed. And also, to find out the appropriate semi-insulating substrate for fabricating the device, SiC lateral p-i-n diodes were fabricated with high purity semi-insulating (HPSI) and vanadium doped semi-insulating (VDSI) substrate and analyzed the electrical characteristics. Based on the results of ion implantation experiments and lateral p-i-n diode analysis, lateral SiC metal-oxide-semiconductor field effect transistors (MOSFETs) were designed and fabricated with HPSI substrate without using an epitaxial layer and electrical characteristics were analyzed. Designed and fabricated SiC lateral MOSFET adopted current path layer (CPL) to replace the drift region between p-base and n+ drain of the conventional MOSFET. Measured effective channel mobility of 21.7 ㎠/V·s was obtained, and high breakdown voltage and low specific on-resistance were achieved. The fabricated MOSFET exhibited a specific on-resistance of 89.9 mΩ·㎠ when LCPL = 20㎛. The maximum breakdown voltage of the MOSFET was 1093 V, yielding a figure of merit (FoM, BV2/㎠) of 13.3 ㎿/㎠. These results show that SiC lateral MOSFETs fabricated on a semi-insulating substrate without using an epitaxial layer is a prospective candidate for power integrated circuits. | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.