repository
Discontinuous PWM Method with Reduced DC-link Ripple Current in Back-to-back Converters
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | Kyo-Beum Lee | - |
| dc.contributor.author | AnatoliiTcai | - |
| dc.date.accessioned | 2018-11-08T08:12:25Z | - |
| dc.date.available | 2018-11-08T08:12:25Z | - |
| dc.date.issued | 2018-02 | - |
| dc.identifier.other | 26815 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/11678 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :전자공학과,2018. 2 | - |
| dc.description.tableofcontents | CHAPTER I. INTRODUCTION 1 CHAPTER II. CONTROL METHODS OF THE VSI. 3 2.1 VSI Topology 3 2.2 Conventional PWM Methods 4 CHAPTER III. PROPOSED DPWM METHOD. 8 CHAPTER IV. SIMULATION RESULTS 14 CHAPTER V. EXPERIMENTAL RESULTS 19 CHAPTER VI. CONCLUSION 23 REFERENCES 24 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | Discontinuous PWM Method with Reduced DC-link Ripple Current in Back-to-back Converters | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 일반대학원 | - |
| dc.contributor.department | 일반대학원 전자공학과 | - |
| dc.date.awarded | 2018. 2 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | 800422 | - |
| dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/jsp/common/DcLoOrgPer.jsp?sItemId=000000026815 | - |
| dc.subject.keyword | Power Electronics | - |
| dc.subject.keyword | Back to back | - |
| dc.subject.keyword | current ripple reduction | - |
| dc.description.alternativeAbstract | This paper introduces a novel discontinuous pulse width modulation (DPWM) method to minimize the dc-link ripple current in back-to-back converters. DPWM is used in power converters to curtail the stress on the switching devices, therefore, extending the lifespan. However, as the conventional DPWM is used in a back-to-back topology, the ripple current of the dc-link severely increases during the regions when the power switches are clamped to the dc-bus. Furthermore, the dc-link ripple current reaches the amplitude value when the power switches of both converters are clamped to different dc-link buses. As a result, the life-span of the dc-link capacitor decreases as it endures more stress. To surmount this issue, the reference voltages should be obtained considering the intervals with the increased ripple current of the dc-link. It is achieved by adjusting the zero-sequence component to match the clamping states of both inverters. The efficacy and performance of the proposed method are demonstrated via the PSIM simulation and the experimental results. | - |
- Appears in Collections:
- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
- Files in This Item:
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
-
- License
- STATISTICS
- Total Visit :3,744,835
- Total Download :1,818
- Today View :22,493
