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Probability-Based Static Wear-Leveling Algorithm for Block and Hybrid-Mapping NAND Flash Memory
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | Tae-Sun Chung | - |
| dc.contributor.author | Gudeta, Yared Hailu | - |
| dc.date.accessioned | 2018-11-08T08:04:28Z | - |
| dc.date.available | 2018-11-08T08:04:28Z | - |
| dc.date.issued | 2013-08 | - |
| dc.identifier.other | 14706 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/10149 | - |
| dc.description | 학위논문(석사)아주대학교 일반대학원 :컴퓨터공학과,2013. 8 | - |
| dc.description.tableofcontents | Probability-Based Static Wear-Leveling Algorithm for Block and Hybrid-Mapping NAND Flash Memory i ACKNOWLEDGEMENTS 2 ABSTRACT 3 TABLE OF CONTENTS 4 LIST OF FIGURES 5 LIST OF TABLES 6 LIST OF ACRONYMS 7 1. Introduction 8 2. Software system architecture of flash memory 12 2.1. Address mapping 12 3. Background and related works 16 3.1. Taxonomy of wear-leveling 16 3.1.1. Dynamic wear-leveling 16 3.1.2. Static wear-leveling 17 3.2. Demonstration of hot/cold identification mechanisms 17 3.3. Advantages and disadvantages of wear-leveling schemes 20 3.4. Related works 21 4. Probability-based wear-leveling algorithm 24 4.1. Markov Chain 24 4.2. Modeling flash memory based on a Markov Chain 24 4.3. The proposed algorithm 31 5. Experimental Results 38 5.1. Simulation Methodology 38 5.2. Simulation Results 40 5.3. Data Migration Overhead 43 5.4. SRAM memory consumption 46 6. Conclusion 48 7. Reference 49 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | Probability-Based Static Wear-Leveling Algorithm for Block and Hybrid-Mapping NAND Flash Memory | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 일반대학원 | - |
| dc.contributor.department | 일반대학원 컴퓨터공학과 | - |
| dc.date.awarded | 2013. 8 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | 571065 | - |
| dc.identifier.url | http://dcoll.ajou.ac.kr:9080/dcollection/jsp/common/DcLoOrgPer.jsp?sItemId=000000014706 | - |
| dc.subject.keyword | Wear-leveling | - |
| dc.description.alternativeAbstract | Owing to its desirable characteristics, flash memory has become attractive to different hardware vendors as a primary choice for data storage. However, because of a limited number of block-erase lifecycles, it has become mandatory to redesign the existing approaches to maximize the flash memory lifetime. Wear-leveling is a mechanism that helps to evenly distribute erase operations to all blocks and enhance lifetime. This research proposes probability-based static wear-leveling. Based on the Markov Chain theory, the future state depends on the present state. Mapping is implemented according to the present visit probability of each logical block in the next state. In each state, the wear-leveling distribution is computed using the standard deviation to determine whether it exceeds the threshold. If it does exceed the threshold, wear-leveling is maintained throughout all blocks in the flash memory by swapping the hot blocks with cold blocks. Using real system-based traces, we have proved that our proposal outperforms the existing design in terms of wear-leveling. | - |
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- Graduate School of Ajou University > Department of Computer Engineering > 3. Theses(Master)
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