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Multivalued logic devices via directly patterned sol-gel metal oxide materials
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 박성준 | - |
| dc.contributor.author | 김원식 | - |
| dc.date.accessioned | 2025-01-25T01:35:55Z | - |
| dc.date.available | 2025-01-25T01:35:55Z | - |
| dc.date.issued | 2023-08 | - |
| dc.identifier.other | 33061 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/24385 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :전자공학과,2023. 8 | - |
| dc.description.tableofcontents | 제1장 Introduction 1 <br> 제1절 Multi-valued logic device fabricated metal oxide semiconductor 1 <br> 제2절 Modulation Vth by UVO treatment 1 <br>제2장 Result and Discussion 4 <br> 제1절 Self-assembled monolayer (SAM) process 4 <br> 제2절 SAM process and photolithography TFTs characteristics 4 <br> 제3절 Modulate metal oxide TFTs Vth via UVO treatment 5 <br> 제4절 Ternary metal oxide inverter 8 <br>제3장 Conclusion 10 <br>제4장 Experimental section 11 <br> 제1절 Materials 11 <br> 제2절 Device fabrication 11 <br> 제3절 UVO treatment 12 <br> 제4절 Characterization 12 <br>제5장 Reference 24 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | Multivalued logic devices via directly patterned sol-gel metal oxide materials | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 대학원 | - |
| dc.contributor.department | 일반대학원 전자공학과 | - |
| dc.date.awarded | 2023-08 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | T000000033061 | - |
| dc.identifier.url | https://dcoll.ajou.ac.kr/dcollection/common/orgView/000000033061 | - |
| dc.subject.keyword | Copper oxide | - |
| dc.subject.keyword | Indium-gallium-zinc oxide | - |
| dc.subject.keyword | Metal oxide transistor | - |
| dc.subject.keyword | Multi-valued logic | - |
| dc.subject.keyword | Self-assembled monolayer | - |
| dc.subject.keyword | Sol-gel process | - |
| dc.description.alternativeAbstract | Recently, significant advancements have been made in the development of multi-valued logic (MVL) devices, including ternary inverters because of the issues of power consumption and processing speed caused by integrated circuits (ICs) integration improvement. In this study, we developed a ternary inverter fabricated by sol-gel metal oxide by self-assembled monolayer (SAM) process. First, we demonstrate that the self-aligned (directly patterned) sol-gel metal oxide process can manufacture thin film transistors (TFTs) on behalf of photolithography. Second, we prove how to control Vth by adjusting the oxygen vacancy of metal oxide channels through UVO treatment. Finally, we fabricate the high- performance metal oxide ternary inverter. These results suggest processes and materials that can fabricate high-performance ternary inverters with metal oxide semiconductors, and the possibility of a large-area process of ternary inverters. | - |
- Appears in Collections:
- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
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